Volantis was founded by serial chip entrepreneur Tapa Ghosh, a Thiel Fellow and member of Y Combinator’s W18 batch. He’s built a career pioneering 3D chips for AI workloads.

Partha Kundu is a technology executive and systems architect specializing in high-performance networking, AI infrastructure, and hyperscale cloud fabric design. He previously served as Architect at Oracle Cloud Infrastructure (OCI), where he led the development of advanced fabric architectures supporting multiple generations of NVIDIA GPUs. His work enabled secure, multi-tenanted, GPU-based bare-metal AI/ML infrastructure at hyperscale and contributed to OCI’s position as a leading cloud platform for large-scale AI workloads. Prior to OCI, as Principal Engineer at Microsoft, Partha drove networking architecture for the MAIA NPU program, defining high-performance interconnect strategy for Microsoft’s next-generation AI accelerators. Earlier, he played a foundational role in architecting the Slingshot fabric at Cray, serving as lead architect and designer of the Cassini NIC. Slingshot powers the world’s Exascale supercomputer systems, which have held the top three positions on the TOP500 rankings since their inception in 2022. Partha has also held senior technical leadership roles across the semiconductor and networking industry, including Technical Director in the HPC business segment at Broadcom, Senior Distinguished Engineer (DE2) in the CTO office at Juniper Networks, and Senior Researcher at Intel Labs, where he helped pioneer the field of Network-on-Chip (NoC) architectures within industry and academia. He is the inventor on 27 granted patents in high-performance networking and scalable systems.

Beth Keser, Ph.D., is a globally recognized leader in semiconductor packaging with over 30 years of industry experience. Previously, Dr. Keser led wafer-level packaging development and product qualification teams at Motorola, Freescale, Qualcomm, and Intel. She is the author of over 50 technical publications, the author of 2 books, and 3 book chapters, and holds 50 patents and patents pending related to advanced electronic packaging technologies. Dr. Keser received her B.S. degree in Materials Science and Engineering from Cornell University and her Ph.D. from the University of Illinois at Urbana-Champaign. She is an IEEE Fellow and an IEEE EPS Distinguished Lecturer who was awarded the 2021 IEEE EPS Exceptional Technical Achievement Award for her seminal contributions and leadership in fan-out wafer-level packaging. In addition, Beth was the President of the International Microelectronics Assembly and Packaging Society (imaps.org) from 2021 to 2023.

Volantis was founded by serial chip entrepreneur Tapa Ghosh, a Thiel Fellow and member of Y Combinator’s W18 batch. He’s built a career pioneering 3D chips for AI workloads, including full idea-to-silicon development for three photonic test chips, all in the AI space.

Mr. Meade is a distinguished technology executive with more than two decades of experience in high-technology industries. He is co-founder and Chief Technology Officer of Volantis Semiconductor, a startup developing wafer-scale AI and high-performance computing platforms integrating silicon photonics, VCSELs, ASICs, and DRAM in advanced 2.5D chip-on-wafer architectures. Previously, he served as Vice President of Manufacturing at Ayar Labs and as Executive Director for Strategic Partnerships at the Texas Institute for Electronics (TIE). Mr. Meade’s educational background includes an MBA from Duke University’s Fuqua School of Business, as well as a Master of Science in Mechanical Engineering and a Bachelor of Mechanical Engineering from the Georgia Institute of Technology. Throughout his career, Mr. Meade has exhibited exceptional innovation and leadership in the domains of photonics, packaging, and memory technologies. His contributions to these fields are evidenced by over 130 patents granted by the United States Patent and Trademark Office (USPTO), encompassing photonics, semiconductor manufacturing, and emerging memory technologies. As an author or co-author of numerous peer-reviewed papers, his work has garnered over 1,300 citations, resulting in an h-index of 22. Mr. Meade has played integral roles in several high-profile research initiatives. Notably, he served as the Principal Investigator (PI) for the DARPA Photonically Optimized Embedded Microprocessors (POEM) program, which achieved the significant milestone of demonstrating the first-ever monolithically integrated bulk CMOS Tx/Rx link. Furthermore, his expertise has been utilized in other prominent research endeavors, including his involvement in the DARPA GRYPHON (Co-PI) and ARPA-e ENLITENED (PI) programs. Most recently, Mr. Meade played a critical role in TIE’s application for the DARPA Next-Generation Microelectronics Manufacturing (NGMM) program, contributing to TIE’s successful award of the $840 million grant. Mr. Meade’s deep expertise in photonics, semiconductor packaging, and advanced computing architectures has made him a sought-after advisor. He has provided strategic and technical consulting to engineering firms, venture capital firms, and other organizations seeking guidance on emerging semiconductor technologies and market opportunities.