Run giant models.

At low latencies.

Run giant models.

At low latencies.

Run giant models.

At low latencies.

>10T Parameter models

>10T Parameter models

>10K tok/s/user

>10K tok/s/user

SRAM-level bandwidth, but with rack-level memory capacity.


Tiny optical waveguides on giant substrates enable memory pools with >30X more bandwidth and >50X bigger size.

SRAM-level bandwidth, but with rack-level memory capacity.


Tiny optical waveguides on giant substrates enable memory pools with >30X more bandwidth and >50X bigger size.

SRAM-level bandwidth, but with rack-level memory capacity.


Tiny optical waveguides on giant substrates enable memory pools with >30X more bandwidth and >50X bigger size.

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Memory

Compute

240

240

TB/s

TB/s

10

10

TB

TB

Backed by Sam Altman, Dylan Patel, Jeff Dean and others. Built by people who pioneered new product categories like co-packaged optics, HBM, and more, from:

> 10 Trillion param models.

SRAM-system latencies.

Reduced $/tok

> 10 Trillion param models. SRAM-system latencies. Reduced $/tok

DeepSeek-V3.2: 1,590 tokens/sec/user on a single chip.

~50 on the fastest GPU.

DeepSeek-V3.2: 1,590 tokens/sec/user on Volantis. ~50 on the fastest GPU.

Explore the Tech

DeepSeek-V3.2

Simulated

1,590

Volantis A-1

1,590

NVDIA B200

50

> 30x

Lower latency for 1T+ models at scale

15x

Tok/$ better serving economics

6x

Tok/W energy efficiency

The Volantis Photonic Design

Volantis builds photonic wires — optical interconnect inside the accelerator. Optical reach is ~100x longer than electrical, so you can put ~100x more memory next to a chip.

Memory Reach

100x

Volantis | Photonic AI Infrastructure for 10T+ Model InferenceELECTRICAL INTERCONNECT5MM LIMITVOLANTIS OPTICAL REACH200MM+

AI is limited by memory, not compute.

AI is limited by memory, not compute.

Electrical wires only reach ~2mm, capping the fast memory you can put next to a chip.

Electrical wires only reach ~2mm, capping the fast memory you can put next to a chip.

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